Designers facing development issues late in the project are often in the unenviable position of having to impose significant delays and expenses to address those problems. It would be great if there was an alternative which could be implemented without requiring a reconfiguration of a significant portion of the board.
In this webinar, you will learn how the new FemtoClock®2 'point-of-use' clock devices from Renesas solve these problems, either by dropping a landing spot right along the clock trace, or even planning in advance, leaving a place where it could be populated if needed. Available in a tiny 4x4 mm package and able to deliver ~ 75 fs of integrated RMS jitter, they can be liberally used throughout a system where board space is tight and coupled noise is a hurdle.
Sr. Staff Marketing Manager
Jeff Keip has spent nearly 25 years specifying, marketing, and developing innovative solutions for clock and timing challenges in the semiconductor industry.